1. Field of Invention
The present invention relates to digital communications, and more particularly to an Analog-to-Digital Converter (ADC) and a Digital-to-Analog Converter (DAC).
2. Description of Related Arts
According to the theoretical analysis, for the communications system, the logarithmic compression law is most ideal but difficult to realize. Conventionally, the communications system employs the companding codes. For example, the audio communications employs the 8-bit companding codes of the A-compression-law and the μ-compression-law whose signal-to-noise ratio (SNR) curves are respectively showed as 1 and 2 in FIG. 1.3, wherein the SNR curves thereof are only approximations to the logarithmic compression law, not ideal SNR curves. Then what shape is the ideal SNR curve supposed to have? The ideal SNR curve satisfies that the SNR does not change with the analog input signal amplitude and the probability density distribution; in other words, the ideal SNR curve is supposed to be a horizontal line 3 as a constant. Furthermore, the ideal SNR curve is supposed to move up and extend right as much as possible, wherein moving the curve up means increasing the SNR and extending the curve right means broadening the signal dynamic range.
Conventionally, the circuit for accomplishing the companding coding is the successive approximation ADC which is slower than the parallel ADC by two orders of magnitude. However, the conventional parallel ADC is unable to accomplish the ideal companding coding. Thus, it becomes the object of the present invention to provide a parallel ADC capable of accomplishing the logarithmic compression law and a correspondent DAC of the logarithmic expansion law.
According to the present invention, the Analog-to-Digital (AD) conversion having a constant SNR is theoretically analyzed as follows.
Firstly, a method for stabilizing an SNR of an ADC at a constant is deduced; a value of the SNR and a signal dynamic range are counted. Given that: a probability density distribution is P(u); when Vj−1<u≦Vj (j=1 . . . Q), a quantizer inputs a signal power Sj and a noise power is Nj; ΔVj=Vj−Vj−1, wherein a quantizer step size of axis V, ΔVj, is a variable; Vj−1 is temporarily taken as a quantized point of u for the analysis,signal average power of u: Sj=∫vj−1Vju2P(u)du  (1.1);noise average power of u: Nj=∫Vj−1Vj(u−Vj−1)2P(u)du  (1.2);SNR: Sj/Nj=∫Vj−1Vju2P(u)du/[∫Vj−1Vj(u−Vj−1)2P(u)du]  (1.3).
Because V0˜VP is divided into Q subzones, ΔVj is small enough and thus P(u) in the interval ΔVj is equal to a constant. Substituted with Vj=Vj−1+ΔVj and X=Vj−1/ΔVj, the SNR is simplified as:Sj/Nj=P(u)∫Vj−1Vju2du/[P(u)∫Vj−1Vj(u−Vj−1)2du]=(3V2j−1*ΔVj+3Vj−1*ΔV2Vj+Δ3Vj)/Δ3Vj=3(X2+X+1/3)=3(X+1/2)2+1/4;  (1.4.1)[Sj/Nj]dB=10 log(3(X+1/2)2+1/4)≈10 log 3+20 log(Vj−1/ΔVj+1/2)  (1.5.1)
If equaling Vj/ΔVj to a constant, the value of Sj/Nj becomes a constant and the object of stabilizing the SNR [Sj/Nj]dB at the constant is accomplished, wherein the [Sj/Nj]dB maintains constant in a range of 20 log VP/VP˜20 log Vθ/VP; in other words, the dynamic range of [Sj/Nj]dB is 0˜20 log Vθ/VP. As showed in FIG. 1.4, given that Vθ=uθ, wherein uθ is a minimal effective signal which a sensor is able to obtain, u is at a signal dead zone when u is at a range of (Vθ˜0); then let the sensor signal u=0 and be merged into a zone y0, Sj/Nj=0.
Then the quantized point is processed with a half-step quantization. In order to determine quantization resistances Rθ˜RQ, Vj−1 is temporarily taken as the quantized point. Once Rθ˜RQ are determined, the quantized point is adjusted into a real quantized point Uj−1=(Vj−1+Vj)/2. Uj−1 is named as a half-step quantized point, and an integral interval of Nj is changed and ranges from Uj−1−ΔVj/2 to Uj−1+ΔVj/2, namely the quantization step size after adjusting the quantized point becomes ΔUj, wherein ΔUj=ΔVj/2. With identical original data, a quantization error decreases ¾ and [Sj/Nj]dB increases 10 log 4=6.02 dB. Here comes the question about how to adjust the quantized point. In the AD conversion process, adjusting the quantized point complicates the circuit; moreover, information after the AD conversion becomes digital, which means it is impossible to adjust the quantized point. Thus the Digital-to-Analog (DA) conversion permits adjusting the quantized point; in other words, during the DA conversion process, the quantized point Vj−1 is adjusted into Uj−1=(Vj−1+Vj)/2. ΔUj=ΔVj/2, substituted with Vj=Vj−1+ΔVj and then X=Vj−1/ΔVj, the SNR is simplified as:Sj/Nj=P(u)∫Uj−1−ΔUjUj−1+ΔUju2du/[P(u)∫Uj−1−ΔUjUj−1+ΔUj(u−Uj−1)2du]=[u3|Uj−1−ΔUjUj−1+ΔUj]/[(u−Uj−1)3|Uj−1−ΔUjUj−1+ΔUj]=3[((Vj−1+Vj)/2)/(ΔVj/2)]2+1=3[((2Vj−1+ΔVj)/2)/(ΔVj/2)]2+1=12(X+1/2)2+1=4[3(X+1/2)2+1/4];  (1.4.2)[Sj/Nj]dB=10 log 4(3(X+1/2)2+1/4)≈10 log 12+20 log(Vj−1/ΔVj+1/2)  (1.5.2)
(1.4.2) is four times of (1.4.1); (1.5.2)=(1.5.1)+10 log 4.
Secondly, how to set Vj and ΔVj, i.e., how to determine the value of each quantized point Vθ, V1 . . . VQ−1, is analyzed. The value of each quantized point depends on a resistance of each resistor in a resistor chain, so a rule about how to set the resistance is simultaneously inferred.
Inference 1: If Vj/ΔVj=a constant, the value of each quantized point Vθ, V1 . . . VQ geometrically increases, namelyV1=Vθ*η1,V2=Vθ*η2 . . . VQ−1=Vθ*ηQ−1,VP=Vθ*ηQ;  (1.6)Proof: Since ΔVj/Vj=(Vj+1−Vj)/Vj=(Vj+1/Vj)−1=a constant  (1.7)Vj+1/Vj=η (η is a geometric constant)  (1.8)Then V1/Vθ=V2/V1= . . . =VQ−1/VQ−2=VP/VQ−1=η  (1.9)
Thus V1, V2 . . . VQ−1 are respectively: V1=Vθ*η1, V2=Vθ*η2 . . . VQ−1=Vθ*ηQ−1, VP=Vθ*ηQ 
Consequently, Conclusion 1: if the value of each quantized point geometrically increases on the basis of potential Vθ, the SNR becomes constant, which means the logarithmic law of compression and expansion are accomplished.
Inference 2 is obtained as a result of the Inference 1.
Inference 2: In order to satisfy a requirement that the value of each quantized point Vθ, V1 . . . VQ geometrically increases, it must be given that{circle around (1)}R1/Rθ=η−1  (1.10);{circle around (2)}Rj+1/Rj=η(j=1 . . . Q−1)  (1.11);
wherein R1, R2 . . . RQ are respectively: R1=Rθ*(η−1), R2=R1*η1, R3=R1*η2 . . . RQ=R1*ηQ−1.
Deduction {circle around (1)}: Since V1=Vθ*η, I(R1+Rθ)=I*Rθ*η, then R1/Rθ=η−1;
Deduction {circle around (2)}: Rθ+ . . . +Rj is simply marked as ΣRj; according to the equation (1.8), Vj+1=Vj*η, namely I*ΣRj+1=I*ΣRj*η, then ΣRj+1−ΣRj=ΣRj*η−ΣRj, Rj+1=ΣRj*(η−1), Rj+1/ΣRj=η−1; also then Rj/ΣRj−1=η−1; thus Rj+1/Rj=ΣRj/ΣRj−1=(Rj+ΣRj−1)/ΣRj−1=Rj/ΣRj−1+ΣRj−1/ΣRj−1=(η−1)+1=η; Q.E.D.
Consequently, Conclusion 2: On the basis of the resistance Rθ, given that R1/Rη=η−1 and Rj+1/Rj=η, wherein η is given a range of (1.001˜1.5) in the present invention, Vj+1/Vj=η; the SNR becomes constant, so that the logarithmic law of compression and expansion are accomplished.
Since VP is known, once two of Vθ, Q and η are determined, the rest one can be determined via deduction. In most cases, Vθ and Q are determined firstly to compute the correspondent η, V1˜VQ−1 and Rθ˜RQ−1.
Conventionally, the audio communications employs the 8-bit digital signals, wherein one bit is for indicating positive or negative and other seven bits are for coding, in such a manner that Q=2q=128, which requires the dynamic range to be no less than 40 dB and the SNR to be no less than 26 dB. As a design of the constant SNR according to the present invention, supposing that VP=10000Δ, wherein Δ is a uniform quantization unit, as showed in Table 1, the SNRs, [Sj/Nj]dB, and the signal dynamic ranges of Vθ=10 Δ, Vθ=5Δ, Vθ=2Δ, Vθ=1Δ and Vθ=0.1Δ are respectively counted according to the equation (1.5.2). Further referring to FIG. 1.5, let a basic potential equal to a potential of the signal dead zone Vθ, if the weak signal zone employs a high SNR, the signal dead zone Vθ is one order of magnitude larger than the few initial quantization steps ΔV1, ΔV2, ΔV3 . . . , which causes a waste of resource; thus it is necessary for Vθ to be at identical order of magnitude with ΔV1, ΔV2, ΔV3 . . . to reduce the signal dead zone, despite of a fact that the SNR within the weak signal zone decreases to some extent. Actually, within the weak signal zone, the signal devices are supposed to focus on detecting and converting. For example, for the weak signals, the radar focuses on finding the target objects as early as possible, when the SNR is allowed to be reasonably low. The SNR increases rapidly along with the strengthened signals; within the medium and strong signal zones, the high SNR is required. The above arrangement of the parameter balances the two features, the SNR [Sj/Nj]dB and the signal dynamic range, to a limit level.
TABLE 1(Vp = 10000Δ; Q = 128)Vθη[Sj/Nj]dBdynamic range 10Δ1.05545 36.1560  5Δ1.06118 35.3266  2Δ1.068834.3374  1Δ1.07461 33.65800.1Δ1.09411 31.72100
An example is listed as follows to illustrate how to accomplish the design of the present invention. Firstly, setting all of the quantized points Vθ˜VQ−1 and determining the quantization resistances Rθ˜RQ based on the parameters listed at the first line of Table 1, wherein the SNR [Sj/Nj]dB=36.15 but the signal dead zone Vθ=10Δ is one order of magnitude larger than the quantization step size ΔV1=0.05545Δ, which causes the waste of resource; secondly, adjusting the signal dead zone Vθ=10Δ into V#θ=Vθ/10=1Δ, namely letting R#θ=Rθ/10, in such a manner that the post-adjusting signal dead zone V#θ=1Δ and the quantization step size ΔV1=0.05545Δ are at the identical order of magnitude, which greatly reduces the signal dead zone; thirdly, computing the SNR to obtain Table 2 based on the post-adjusting equation[Sj/Nj]dB=10 log 4(3(X+1/2)2+1/4)≈10.792+20 log(V#j−1/ΔVj+1/2)  (1.5.3),
wherein it is confirmed that the minimal SNR is within an available range, as well as that the SNR increases rapidly with the strengthening of the signal and quickly gets close to the maximum value 36.15. The dynamic range including the section of low SNR expands into 80 dB after the adjusting from the previous 60 dB, as showed in Table 2.
TABLE 2Vθ = 10Δ; η = 1.05545; V#θ = 1Δ; [Sj/Nj]dB = 36.15 dB; dynamic range = 80 dBjVj−1ΔVjV#j−1 V#j−1/ΔVj[Sj/Nj]dB110.000.5551.0001.80318.04210.550.5851.5552.65620.78311.14 0.6182.1403.46422.75411.76 0.6522.7574.23024.29512.41 0.6883.4094.95525.53613.10 0.7264.0975.46226.56713.820.7674.8246.29327.43814.590.8095.590 6.91028.19915.400.8546.399 7.49428.8510 16.250.9017.253 8.04829.4311 17.150.9518.154 8.57329.9512 18.111.0049.119.0730.4113 19.111.06010.119.5430.831420.171.11811.179.9931.2015 21.291.18012.29 10.4131.5516 22.471.24613.47 10.8131.86The following are some illustrations about the present invention.                The multi-stage parallel super-high-speed ADC and DAC of the logarithmic companding law, provided by the present invention, are respectively simplified as the logarithmic ADC and the logarithmic DAC; the logarithmic ADC and the logarithmic DAC together are named as the logarithmic ADDA; sub-stages of the logarithmic ADC, the logarithmic DAC and the logarithmic ADDA are respectively simplified as sub-ADC, sub-DAC, sub-ADDA; two and more than two sub-stages are defined as multi-stage; the logarithmic ADDA comprises the multi-sub-ADDAs; AD##, DA##, A##D, AD#, DA# and A#D are respectively symbols of the logarithmic ADC, the logarithmic DAC, the logarithmic ADDA, the sub-ADC, the sub-DAC and the sub-ADDA.        λ is a wildcard character substituted for α, β, γ . . . ; in order to avoid conflicts of numbering, α, β, γ . . . actually represent 1, 2, 3 . . . ; stage α, stage β, stage γ . . . respectively represent stage 1, stage 2, stage 3 . . . , wherein stage m is the last stage; stage λ has a conversion bit of qλ; μ=λ+1 represents the next stage of λ.        Stage α is the top stage, namely the stage α corresponds to the highest qα bit of N-bit binaries; the bit numbers respectively correspondent to stage β, stage γ . . . decrease successively; for example, N=4 stages*3 bits=12 bits; the three bits, Dα2Dα1Dα0, of stage α correspond to the highest D11D10D9 bit; the three bits, Dβ2Dβ1Dβ0, of stage β correspond to the second high D8D7D6 bit . . . .        The stage-potential switch JDWKG comprises the multi-channel switches DLKG and the threshold switches LJKG. The two types of switches are equivalent, so any illustration about the one type applies to the other type.        For the logarithmic ADC, the alternating analog voltage signal, represented by the lowercase uαy, only appears before the front-end circuit at the stage α; Uλy represents the positive fluctuating analog voltage signal inputted at the stage λ which is simplified as the input voltage Uλy thereafter; the inputted voltage Uλy is converted into the stage-potential VλG, and then the stage-potential VλG is converted into the digital signal Dλ(q−1) . . . Dλ0 wherein the stage-potential VλG works as a bridge.        For the logarithmic DAC, the digital signal at the stage λ Dλ(q−1) . . . Dλ0 is converted into the stage-potential; through proportional attenuation, the stage-potential becomes the outputted positive analog voltage signal, or the output voltage for short.        The input voltage and the output voltage together are called the analog voltage.        Hereafter, the sub-stage all-parallel ADC is called the parallelizer for short; the sampling/holding device is called the sampler/holder CB for short.        The specifically embodied circuits are various, and the circuit illustrated in the present invention is only exemplary.        The nature of the symbol remains regardless of the subscripts; for example, CB is the sampler/holder and CBβ is still the sampler/holder, wherein the subscript β is only the stage footnote; the subscript (Q−1)˜0 represents step (Q−1)˜step 0; the subscript (T−1)˜0 represents step (T−1)˜step 0; the subscript (q−1)˜0 represents bit (q−1)˜bit 0; the subscript (t−1) represents bit (t−1)˜bit 0; the subscripts α, β and γ represent the stage, and λ is the wildcard character for each stage.        The circuit within the solid frame or the dashed frame is the module whose name is provided at the corner.        The control characters I*λg and Iλg are connected with wires, i.e., I*λg=Iλg; thus I*λg and Iλg refer to the same control character; Iλg is showed at the output terminal of the comparator, and Iλg is showed at the control terminal of the threshold switch.        If the defined symbol, such as V1, is given a renewed definition, the symbol represents the renewed definition thereafter.        The voltage follower, abbreviated as follower, is the integrated operational amplifier (integrated op-amp) having the short connection of the inverting input terminal (abbreviated as the inverting terminal) and the output terminal. One skilled in the electronics understands that the signal is inputted via the non-inverting input terminal (abbreviated as the non-inverting terminal) and that the voltage of the output terminal accurately follows and equals the inputted signal. In other words, the voltage drop of the signal voltage from the input terminal to the output terminal is extremely small (smaller than 10−8V); technically speaking, the voltage drop is zero, or the on-resistance is zero. Meanwhile, the input resistance is extremely larger (as large as 109Ω); technically speaking, the input resistance is infinitely great. The follower is represented by a triangle without any number.        The input signal voltage and the output signal voltage of the voltage follower switch, or the follower switch for short, have the effective intervals. All the signal voltages mentioned in the present invention are within the effective intervals. The follower switch has various logic relations, and the threshold switch is one type of the follower switch.        The threshold switch Sλg represents the threshold switch at the step g, stage λ. Sλg has the upper control character Iλ(g+1) and the lower control character Iλg. The step number at each stage can be different; the variable symbol of the step number at each stage is uniformly represented by g, only for convenience.        In order to simplify the illustration, the present invention makes following appointments. The reference points Vλ(Q−1)˜Vλ1 are correspondently connected to the inverting terminals of the comparators Cλ(Q−1)˜Cλ1; the to-be-compared analog voltage UλZ, or the to-be-compared voltage for short, are connected to the non-inverting terminals of the comparators Cλ(Q−1)˜Cλ1; the positive logic is adopted, wherein “1” represents that UλZ is higher than the reference voltage and “0” represents that UλZ is lower than the reference voltage; for example, supposing that the stage λ has a threshold point G, for the to-be-compared voltage at stage λUλZ>(VλG˜Vλ0), the control characters IλG˜Iλ0 correspondent to the reference points VλG˜Vλ0 are equal to 1; and for UλZ<(VλQ˜Vλ(G+1)), the control characters IλG˜Iλ(G+1) correspondent to the reference points VλG˜Vλ(G+1) are equal to zero. The opposite appointment is also acceptable.        